Table 1. Revision History (continued)
DescriptionRevisionDate
– Corrected figure ADC Input Equivalency.
– Removed Dither Enable bit and corrected reset for ADCCTL register.
■ In the UART chapter, clarified that for a receive timeout, the RTIM bit in the UARTIM register must
be set to see the RTMIS and RTRIS status in the UARTMIS and UARTRIS registers.
■ In the SSI chapter:
Clarified Receive FIFO operation.–
– Clarified DMA operation.
– Removed End of Transmission (EOT) bit 4 from QSSI Control 1 (SSICR1) register.
■ In the Ethernet chapter, clarified Initialization and Configuration.
■ In the USB chapter, added important note that when configured as a bus-powered Device, the USB
can operate in SUSPEND mode but produces a higher power draw than required to be compliant.
■ In the Electrical Characteristics chapter:
In Reset Characteristics table, updated internal reset time parameter values.–
– In PIOSC Clock Characteristics table, updated parameter values.
– In Hibernation External Oscillator (XOSC) Input Characteristics table, removed parameter C0
Crystal shunt capacitance.
– Updated Crystal Parameters table.
– In Hibernation Module Tamper I/O Characteristics table, updated TMPRn pull-up resistor
parameter values.
– In Flash Memory Characteristics table, updated T
PROG64
nom value.
– In EEPROM Characteristics table, added values for Read access time and removed EEPROM
recovery Power-On Reset delay parameter.
– In EPI PSRAM Interface Characteristics table, updated Min value for EPI_CLK period.
– In ADC Electrical Characteristics at 1 Msps table, updated values for V
ADCIN
parameter.
– Corrected ADC Input Equivalency diagram.
– In Bi- and Quad-SSI Characteristics table, added clarifying footnotes.
– Added PWM Timing Characteristics table.
– Updated Current Consumption table.
– In Peripheral Current Consumption table, updated I
DDEMAC
Nom value.
■ In Package Information appendix:
Updated Orderable Devices section to reflect silicon revision 3 part numbers.–
– Added Device Nomenclature section.
– Deleted packaging materials section and put into separate document.
■ Additional minor data sheet clarifications and corrections.
15638.2711December 2013 ■ Changed NDA (Non-Disclosure Agreement) footer to indicate NDA only applies to USB content.
■ In System Control chapter:
Added sections "Optional Clock Output Signal (DIVSCLK)" and "Hardware System Service
Request".
–
– Removed some registers and bits:
• LDORDRIS bit from Raw Interrupt Status (RIS) register, LDORDIM bit from Interrupt Mask
Control (IMC) register, and LDORDMIS bit from Masked Interrupt Status and Clear (MISC)
register
• Deep Sleep Mode Memory Timing Register 0 for Main Flash and EEPROM
(DSMEMTIM0) register
• LDO Power Calibration (LDOPCAL) register
• LDO Sleep Power Control (LDOSPCTL) register
• LMINERR bit from Sleep/Deep-Sleep Power Mode Status (SDPMST) register
– Added LDOSME, TSPDE, PIOSCPDE, SRAMSM, SRAMLPM, FLASHLPM, and LDOSEQ bits in
SYSPROP register.
■ In Internal Memory chapter:
June 18, 201446
Texas Instruments-Production Data
Revision History
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