■ Power-Down: Most of the PLL internal circuitry is disabled and the PLL does not drive the output.
The modes are programmed using the PLLPWR bit in the PLLFREQ0 register (see page 292).
PLL Configuration
The PLL is disabled by default during power-on reset and is enabled later by software if required.
Software specifies the output divisor to set the system clock frequency and enables the PLL to drive
the output. The PLL is controlled using the PLLFREQ0, PLLFREQ1 and PLLSTAT registers.
Changes made to these registers do not become active until after the NEWFREQ bit in the RSCLKCFG
register is enabled.
The clock source for the main PLL is selected by configuring the PLLSRC field in the Run and Sleep
Clock Configuration (RSCLKCFG) register.
The PLL allows for the generation of system clock frequencies in excess of the reference clock
provided. The reference clocks for the PLL are the PIOSC and the MOSC. The PLL is controlled
by two registers, PLLFREQ0 and PLLFREQ1. The PLL VCO frequency (f
VCO
) is determined through
the following calculation:
f
VCO
= f
IN
* MDIV
where
f
IN
= f
XTAL
/(Q+1)(N+1) or f
PIOSC
/(Q+1)(N+1)
MDIV = MINT + (MFRAC / 1024)
The Q and N values are programmed in the PLLFREQ1 register. Note that to reduce jitter, MFRAC
should be programmed to 0x0.
When the PLL is active, the system clock frequency (SysClk) is calculated using the following
equation:
SysClk = f
VCO
/ (PSYSDIV + 1)
The PLL system divisor factor (PSYSDIV) determines the value of the system clock. Table
5-6 on page 237 shows how the system divisor encodings affect the system clock frequency when
the f
VCO
= 480 MHz.
Table 5-6. System Divisor Factors for f
vco
=480 MHz
f
VCO
(MHz)= 480 MHz
System Clock (SYSCLK) (MHz)
System Divisors (PSYSDIV +1)
a
4120
860
1048
1630
2024
4012
806
a. The use of non-integer divisors introduce additional jitter which may affect interface performance.
237June 18, 2014
Texas Instruments-Production Data
Tiva
™
TM4C1294NCPDT Microcontroller
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