Register 125: Watchdog Timer Deep-Sleep Mode Clock Gating Control
(DCGCWD), offset 0x800
The DCGCWD register provides software the capability to enable and disable watchdog modules
in deep-sleep mode. When enabled, a module is provided a clock. When disabled, the clock is
disabled to save power.
Important: This register should be used to control the clocking for the watchdog modules.
Watchdog Timer Deep-Sleep Mode Clock Gating Control (DCGCWD)
Base 0x400F.E000
Offset 0x800
Type RW, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
D0D1reserved
RWRWROROROROROROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved31:2
Watchdog Timer 1 Deep-Sleep Mode Clock Gating Control
DescriptionValue
Watchdog module 1 is disabled in deep-sleep mode.0
Enable and provide a clock to Watchdog module 1 in deep-sleep
mode.
1
0RWD11
Watchdog Timer 0 Deep-Sleep Mode Clock Gating Control
DescriptionValue
Watchdog module 0 is disabled in deep-sleep mode.0
Enable and provide a clock to Watchdog module 0 in deep-sleep
mode.
1
0RWD00
427June 18, 2014
Texas Instruments-Production Data
Tiva
™
TM4C1294NCPDT Microcontroller
To Next Page
Loading...
Need help?
General
