27.7 Reset
Table 27-14. Reset Characteristics
a
UnitMaxNomMinParameter NameParameterParameter
No.
µs126-0.44Digital POR to Internal Reset assertion
delay
c
T
DPORDLY
b
R1
ms1614-Standard Internal Reset time
T
IRTOUT
bd
R2
ms6400
f
-24.4Internal Reset time with recovery code repair
(program or erase)
e
µs125-0.44BOR0 to Internal Reset assertion delay
c
T
BOR0DLY
b
R3
µs-0.25
g
/100
h
-Minimum RST pulse widthT
RSTMIN
R4
µs-0.85-RST to Internal Reset assertion delayT
IRHWDLY
R5
µs-2.44-Internal reset timeout after software-initiated
system reset
T
IRSWR
b
R6
µs-2.44-Internal reset timeout after Watchdog resetT
IRWDR
b
R7
µs-2.44-Internal reset timeout after MOSC failure
reset
T
IRMFR
b
R8
a. Minimum timings are for reset assertion using PIOSC as a clock source. Maximum timings are for reset assertion using
LFIOSC in Deep-Sleep Operation.
b. These values are based on simulation.
c. Timing values are dependent on the V
DD
power-down ramp rate.
d. This is the delay from the time POR is released until the reset vector is fetched.
e. This parameter applies only in situations where a power-loss or brown-out event occurs during an EEPROM program or
erase operation, and EEPROM needs to be repaired (which is a rare case). For all other sequences, there is no impact
to normal Power-On Reset (POR) timing. This delay is in addition to other POR delays.
f. This value represents the maximum internal reset time when the EEPROM reaches its endurance limit.
g. Standard operation.
h. Deep-Sleep operation with PIOSC powered down.
Figure 27-9. Digital Power-On Reset Timing
Reset
(Internal)
R2
Digital POR
R
1
The digital Power-On Reset is only released when the analog Power-On Reset has deasserted and
all of the Power-OK monitors for each of the supplies indicate that power levels are in operational
ranges.
1831June 18, 2014
Texas Instruments-Production Data
Tiva
™
TM4C1294NCPDT Microcontroller
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