Texas Instruments TM4C1294NCPDT User Manual

with internal FIFO memories allowing up to eight 16-bit values to be stored independently in both
transmit and receive modes. The QSSI also supports the µDMA interface. The transmit and receive
FIFOs can be programmed as destination/source addresses in the µDMA module. µDMA operation
is enabled by setting the appropriate bit(s) in the SSIDMACTL register (see page 1260).
17.3.1 Bit Rate Generation
The QSSI includes a programmable bit rate clock divider and prescaler to generate the serial output
clock. Bit rates are supported to 2 MHz and higher, although maximum bit rate is determined by
peripheral devices.
The serial bit rate is derived by dividing down the input clock (SysClk). The clock is first divided by
an even prescale value CPSDVSR from 2 to 254, which is programmed in the SSI Clock Prescale
(SSICPSR) register (see page 1252). The clock is further divided by a value from 1 to 256, which is
1 + SCR, where SCR is the value programmed in the SSI Control 0 (SSICR0) register (see page 1245).
The frequency of the output clock SSInClk is defined by:
SSInClk = SysClk / (CPSDVSR * (1 + SCR))
Note: SYSCLK or ALTCLK is used as the source for the SSInClk depending on how the CS field
in the SSI Clock Configuration (SSICC) register is configured. For master legacy mode,
the SYSCLK or ALTCLK must be at least two times faster than the SSInClk, with the
restriction that SSInClk cannot be faster than 60 MHz. For slave mode, SYSCLK or ALTCLK
must be at least 12 times faster than the SSInClk. In slave legacy mode, the maximum
frequency of SSInClk is 10 MHz.
See “Synchronous Serial Interface (SSI)” on page 1867 to view legacy SSI and QSSI timing parameters.
17.3.2 FIFO Operation
17.3.2.1 Transmit FIFO
The common transmit FIFO is a 16-bit wide, 8-locations deep, first-in, first-out memory buffer. The
CPU writes data to the FIFO by writing the SSI Data (SSIDR) register (see page 1249), and data is
stored in the FIFO until it is read out by the transmission logic.
When configured as a master or a slave, parallel data is written into the transmit FIFO prior to a
legacy SSI serial conversion and transmission to the attached slave or master, respectively, through
the SSInDAT0/SSInTX pin.
In slave mode, the legacy SSI transmits data each time the master initiates a transaction. If the
transmit FIFO is empty and the master initiates, the slave transmits the 8th most recent value in the
transmit FIFO. If less than 8 values have been written to the transmit FIFO since the SSI module
clock was enabled using the Rn bit in the RCGCSSI register or if the QSSI is reset using the SRSSI
register, then 0 is transmitted. Care should be taken to ensure that valid data is in the FIFO as
needed. The QSSI can be configured to generate an interrupt or a µDMA request when the FIFO
is empty.
Note: When operating in Legacy Mode, the QuadSSI's SSInXDAT0 signal functions as SSInTX.
17.3.2.2 Receive FIFO
The common receive FIFO is a 16-bit wide, 8-locations deep, first-in, first-out memory buffer.
Received data using the legacy serial interface is stored in the buffer until read out by the CPU,
which accesses the read FIFO by reading the SSIDR register. If the receive FIFO is full when the
master or slave receives new data, the data is held off until the receive FIFO has space.
1229June 18, 2014
Texas Instruments-Production Data
Tiva
™
TM4C1294NCPDT Microcontroller

Texas Instruments TM4C1294NCPDT Specifications

General

Brand	Texas Instruments
Model	TM4C1294NCPDT
Category	Microcontrollers
Language	English