Register 2: GPIO Direction (GPIODIR), offset 0x400
The GPIODIR register is the data direction register. Setting a bit in the GPIODIR register configures
the corresponding pin to be an output, while clearing a bit configures the corresponding pin to be
an input. All bits are cleared by a reset, meaning all GPIO pins are inputs by default.
GPIO Direction (GPIODIR)
GPIO Port A (AHB) base: 0x4005.8000
GPIO Port B (AHB) base: 0x4005.9000
GPIO Port C (AHB) base: 0x4005.A000
GPIO Port D (AHB) base: 0x4005.B000
GPIO Port E (AHB) base: 0x4005.C000
GPIO Port F (AHB) base: 0x4005.D000
GPIO Port G (AHB) base: 0x4005.E000
GPIO Port H (AHB) base: 0x4005.F000
GPIO Port J (AHB) base: 0x4006.0000
GPIO Port K (AHB) base: 0x4006.1000
GPIO Port L (AHB) base: 0x4006.2000
GPIO Port M (AHB) base: 0x4006.3000
GPIO Port N (AHB) base: 0x4006.4000
GPIO Port P (AHB) base: 0x4006.5000
GPIO Port Q (AHB) base: 0x4006.6000
Offset 0x400
Type RW, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
DIRreserved
RWRWRWRWRWRWRWRWROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0000.00ROreserved31:8
GPIO Data Direction
DescriptionValue
Corresponding pin is an input.0
Corresponding pins is an output.1
0x00RWDIR7:0
June 18, 2014760
Texas Instruments-Production Data
General-Purpose Input/Outputs (GPIOs)