DescriptionResetTypeNameBit/Field
Divide-by-Zero Usage Fault
DescriptionValue
No divide-by-zero fault has occurred, or divide-by-zero trapping
is not enabled.
0
The processor has executed an SDIV or UDIV instruction with
a divisor of 0.
1
When this bit is set, the PC value stacked for the exception return points
to the instruction that performed the divide by zero.
Trapping on divide-by-zero is enabled by setting the DIV0 bit in the
Configuration and Control (CFGCTRL) register (see page 175).
This bit is cleared by writing a 1 to it.
0RW1CDIV025
Unaligned Access Usage Fault
DescriptionValue
No unaligned access fault has occurred, or unaligned access
trapping is not enabled.
0
The processor has made an unaligned memory access.1
Unaligned LDM, STM, LDRD, and STRD instructions always fault
regardless of the configuration of this bit.
Trapping on unaligned access is enabled by setting the UNALIGNED bit
in the CFGCTRL register (see page 175).
This bit is cleared by writing a 1 to it.
0RW1CUNALIGN24
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved23:20
No Coprocessor Usage Fault
DescriptionValue
A usage fault has not been caused by attempting to access a
coprocessor.
0
The processor has attempted to access a coprocessor.1
This bit is cleared by writing a 1 to it.
0RW1CNOCP19
Invalid PC Load Usage Fault
DescriptionValue
A usage fault has not been caused by attempting to load an
invalid PC value.
0
The processor has attempted an illegal load of EXC_RETURN
to the PC as a result of an invalid context or an invalid
EXC_RETURN value.
1
When this bit is set, the PC value stacked for the exception return points
to the instruction that tried to perform the illegal load of the PC.
This bit is cleared by writing a 1 to it.
0RW1CINVPC18
185June 18, 2014
Texas Instruments-Production Data
Tiva
™
TM4C1294NCPDT Microcontroller
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