Texas Instruments TM4C1294NCPDT User Manual

The application can identify the type of BOR event that occurred by reading the Power-Temperature
Cause (PWRTC) register. The BOR detection circuits can be programmed to generate a reset,
System Control interrupt, or NMI in the Power-Temp Brown Out Control (PTBOCTL) register.
The default settings at reset are as follows:
■ V
DDA
under BOR detection default setting is for no action to occur.
■ V
DD
under BOR detection default setting is to execute a full POR.
If the user has programmed a field in the PTBOCTL to generate a reset, then the BOR bit of the
Reset Behavior Control (RESBEHAVCTL) register can be programmed to further define what
type of reset is generated. If the BOR field is programmed to 0x3, a full POR is initiated; if is set to
0x2, then a system reset is issued. When the BOR field is set to a 0x0 or 0x1, then the Brown-Out
detection circuit will perform its default operation upon assertion, which is issuing an interrupt.
Note: V
DDA
BOR and V
DD
BOR events are a combined BOR to the system logic, such that if either
BOR event occurs, the following bits are affected:
■ BORRIS bit in the Raw Interrupt Status (RIS) register, System Control offset 0x050.
See page 261.
■ BORMIS bit in the Masked Interrupt Status and Clear (MISC) register, System Control
offset 0x058. This bit is set only if the BORIM bit in the Interrupt Mask Control (IMC)
register has been set. See page 263 and page 265.
■ BOR bit in the Reset Cause (RESC) register, System Control offset 0x05C. This bit is
set only if either of the BOR events have been configured to initiate a reset. See page 267.
In addition, the following bits control both BOR events:
■ BORIM bit in the Interrupt Mask Control (IMC) register, System Control offset 0x054.
■ VDDA_UBOR0 and VDD_UBOR0 bits in the Power-Temperature Cause (PWRTC) register.
Please refer to “System Control” on page 220 for more information on how to configure these
registers.
The brown-out POR reset sequence is as follows:
1. When one of the BOR event triggers occurs, an internal Brown-Out Reset condition is set.
2. If the BOR event has been programmed to generate a reset in the PTBOCTL register and the
BOR bit of the RESBEHAVCTL has been set to 0x3, an internal POR reset is asserted.
3. The internal reset is released and the core executes a full initialization of the device. Upon
completion, the core loads from memory the initial stack pointer, the initial program counter,
and the first instruction designated by the program counter, and then begins execution. The
application starts after deassertion of internal POR. Refer to “Reset” on page 1831 for BOR internal
reset deassertion timing.
The brown-out system reset sequence is as follows:
1. When one of the BOR event triggers occurs, an internal Brown-Out Reset condition is set.
2. If the BOR event has been programmed to generate a reset in the PTBOCTL register and the
BOR bit of the RESBEHAVCTL has been set to 0x2, an internal reset is asserted.
225June 18, 2014
Texas Instruments-Production Data
Tiva
™
TM4C1294NCPDT Microcontroller

Texas Instruments TM4C1294NCPDT Specifications

General

Brand	Texas Instruments
Model	TM4C1294NCPDT
Category	Microcontrollers
Language	English