Register 24: DMA Channel Map Select 2 (DMACHMAP2), offset 0x518
Each 4-bit field of the DMACHMAP2 register configures the μDMA channel assignment as specified
in Table 9-1 on page 680.
Note: To support legacy software which uses the DMA Channel Assignment (DMACHASGN)
register, a value of 0x0 is equivalent to a DMACHASGN bit being clear, and a value of 0x1
is equivalent to a DMACHASGN bit being set.
DMA Channel Map Select 2 (DMACHMAP2)
Base 0x400F.F000
Offset 0x518
Type RW, reset 0x0000.0000
16171819202122232425262728293031
CH20SELCH21SELCH22SELCH23SEL
RWRWRWRWRWRWRWRWRWRWRWRWRWRWRWRWType
0000000000000000Reset
0123456789101112131415
CH16SELCH17SELCH18SELCH19SEL
RWRWRWRWRWRWRWRWRWRWRWRWRWRWRWRWType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
μDMA Channel 23 Source Select
See Table 9-1 on page 680 for channel assignments.
0x00RWCH23SEL31:28
μDMA Channel 22 Source Select
See Table 9-1 on page 680 for channel assignments.
0x00RWCH22SEL27:24
μDMA Channel 21 Source Select
See Table 9-1 on page 680 for channel assignments.
0x00RWCH21SEL23:20
μDMA Channel 20 Source Select
See Table 9-1 on page 680 for channel assignments.
0x00RWCH20SEL19:16
μDMA Channel 19 Source Select
See Table 9-1 on page 680 for channel assignments.
0x00RWCH19SEL15:12
μDMA Channel 18 Source Select
See Table 9-1 on page 680 for channel assignments.
0x00RWCH18SEL11:8
μDMA Channel 17 Source Select
See Table 9-1 on page 680 for channel assignments.
0x00RWCH17SEL7:4
μDMA Channel 16 Source Select
See Table 9-1 on page 680 for channel assignments.
0x00RWCH16SEL3:0
731June 18, 2014
Texas Instruments-Production Data
Tiva
™
TM4C1294NCPDT Microcontroller
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