Figure 8-6. Prefetch Fills from Flash
0
WORD 7 WORD 6 WORD 5 WORD 4 WORD 3 WORD 2 WORD 1 WORD 0
WORD 6 WORD 5 WORD 4 WORD 3 WORD 2 WORD 1 WORD 0WORD 7
Prefetch
Buffer 0
Prefetch
Buffer 1
255 127 96 95 64 63 32 31128159160191192223224
WORD 7 WORD 6 WORD 5 WORD 4 WORD 3 WORD 2 WORD 1 WORD 0
WORD 6 WORD 5 WORD 4 WORD 3 WORD 2 WORD 1 WORD 0WORD 7
Prefetch
Buffer 2
Prefetch
Buffer 3
TAG
TAG
TAG
TAG
WAIT
STATES
1 2 3 4 5 6 7
EVENT AEVENT BEVENT C
EVENT D
Least
Recently
Used
Buffer
Note that if the CPU target word is beyond Word 2 (Word 3 through Word 7) then the next prefetch
fill begins immediately and, depending on the CPU frequency, a delay is incurred between CPU
access of Word 7 and Word 0 of the next line.
Note: For optimal prefetch buffer performance, align application code/branches on 8-word
boundaries.
Note: Because the prefetch buffers and Flash memory can effectively be utilized at 20 Mhz and
above, an application may see an improvement in current consumption from 16 MHz to 20
MHz.
The prefetch buffers can be forced ON and OFF by setting the FPFON and FPFOFF bits in the Flash
Configuration (FLASHCONF) register at 0xFC8. If the application sets the FPFON or FPFOFF bit
while the CPU is currently reading or writing to Flash, the prefetch buffer action of turning on or off
happens only after the Flash operation has completed. This feature can be used in test modes when
determining optimum memory configuration for code.
Prefetch buffer valid tags can be cleared in the following ways:
■ Any Flash Configuration (FLASHCONF) register changes, such as:
– Disabling the prefetch buffer by setting the FPFOFF bit
– Setting the CLRTV bit to clear the prefetch buffer tags
■ A system reset
■ ROM accesses
■ Error during ICODE accesses
■ System aborts
■ Mirror mode changes
Note: If the prefetch buffers are enabled and application code branches to a location other than
flash memory which then modifies the flash memory, the prefetch tags must be cleared
before returning to flash code execution. Prefetch buffer valid tags can be cleared by setting
the CLRTV bit in the FLASHCONF register.
8.2.3.3 Flash Mirror Mode
Flash mirroring allows multiple copies of software to exist in Flash simultaneously. The software
can run from the lower banks at the same time software is updating a mirrored copy on the upper
bank. In addition to the data, the boot loader in both the lower and upper banks must be mirrored
June 18, 2014608
Texas Instruments-Production Data
Internal Memory
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