Register 168: Hibernation Peripheral Ready (PRHIB), offset 0xA14
The PRHIB register indicates whether the Hibernation module is ready to be accessed by software
following a change in status of power, Run mode clocking, or reset. A power change is initiated if
the corresponding PCHIB bit is changed from 0 to 1. A Run mode clocking change is initiated if the
corresponding RCGCHIB bit is changed. A reset change is initiated if the corresponding SRHIB bit
is changed from 0 to 1.
The PRHIB bit is cleared on any of the above events and is not set again until the module is
completely powered, enabled, and internally reset.
Hibernation Peripheral Ready (PRHIB)
Base 0x400F.E000
Offset 0xA14
Type RO, reset 0x0000.0001
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
R0reserved
ROROROROROROROROROROROROROROROROType
1000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved31:1
Hibernation Module Peripheral Ready
DescriptionValue
The Hibernation module is not ready for access. It is unclocked,
unpowered, or in the process of completing a reset sequence.
0
The Hibernation module is ready for access.1
1ROR00
June 18, 2014504
Texas Instruments-Production Data
System Control
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