Register 12: DMA Channel Request Mask Set (DMAREQMASKSET), offset
0x020
Each bit of the DMAREQMASKSET register represents the corresponding μDMA channel. Setting
a bit disables μDMA requests for the channel. Reading the register returns the request mask status.
When a μDMA channel's request is masked, that means the peripheral can no longer request μDMA
transfers. The channel can then be used for software-initiated transfers.
DMA Channel Request Mask Set (DMAREQMASKSET)
Base 0x400F.F000
Offset 0x020
Type RW, reset 0x0000.0000
16171819202122232425262728293031
SET[n]
RWRWRWRWRWRWRWRWRWRWRWRWRWRWRWRWType
0000000000000000Reset
0123456789101112131415
SET[n]
RWRWRWRWRWRWRWRWRWRWRWRWRWRWRWRWType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Channel [n] Request Mask Set
DescriptionValue
The peripheral associated with channel [n] is enabled to request
μDMA transfers.
0
The peripheral associated with channel [n] is not able to request
μDMA transfers. Channel [n] may be used for software-initiated
transfers.
1
Bit 0 corresponds to channel 0. A bit can only be cleared by setting the
corresponding CLR[n] bit in the DMAREQMASKCLR register.
0x0000.0000RWSET[n]31:0
719June 18, 2014
Texas Instruments-Production Data
Tiva
™
TM4C1294NCPDT Microcontroller
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