Texas Instruments TM4C1294NCPDT User Manual

Register 46: ADC Sample Sequence 3 Sample and Hold Time (ADCSSTSH3),
offset 0x0BC
This register controls the sample period size for the sample in sequencer 3. The sample and hold
period select specifies the time allocated to the sample and hold circuit as shown by the encodings
in Table 15-3 on page 1058
Note: If sampling the internal temperature sensor, the sample and hold width should be at least
16 ADC clocks (TSHn = 0x4).
Table 15-10. Sample and Hold Width in ADC Clocks
N
SH
TSHn Encoding
40x0
reserved0x1
80x2
reserved0x3
160x4
reserved0x5
320x6
reserved0x7
640x8
reserved0x9
1280xA
reserved0xB
2560xC
reserved0xD-0xF
ADC Sample Sequence 3 Sample and Hold Time (ADCSSTSH3)
ADC0 base: 0x4003.8000
ADC1 base: 0x4003.9000
Offset 0x0BC
Type RW, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
TSH0reserved
RWRWRWRWROROROROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0ROreserved31:4
1st Sample and Hold Period Select
The TSH0 field is used during the first sample of a sequence executed
with the sample sequencer.
0x0RWTSH03:0
1147June 18, 2014
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TM4C1294NCPDT Microcontroller

Texas Instruments TM4C1294NCPDT Specifications

General

Brand	Texas Instruments
Model	TM4C1294NCPDT
Category	Microcontrollers
Language	English