1.3.6.6 Watchdog Timers (see page 1028)
A watchdog timer is used to regain control when a system has failed due to a software error or to
the failure of an external device to respond in the expected way. The TM4C1294NCPDT Watchdog
Timer can generate an interrupt, a non-maskable interrupt, or a reset when a time-out value is
reached. In addition, the Watchdog Timer is ARM FiRM-compliant and can be configured to generate
an interrupt to the microcontroller on its first time-out, and to generate a reset signal on its second
timeout. Once the Watchdog Timer has been configured, the lock register can be written to prevent
the timer configuration from being inadvertently altered.
The TM4C1294NCPDT microcontroller has two Watchdog Timer modules: Watchdog Timer 0 uses
the system clock for its timer clock; Watchdog Timer 1 uses the PIOSC as its timer clock. The
Watchdog Timer module has the following features:
■ 32-bit down counter with a programmable load register
■ Separate watchdog clock with an enable
■ Programmable interrupt generation logic with interrupt masking and optional NMI function
■ Lock register protection from runaway software
■ Reset generation logic with an enable/disable
■ User-enabled stalling when the microcontroller asserts the CPU Halt flag during debug
1.3.6.7 Programmable GPIOs (see page 742)
General-purpose input/output (GPIO) pins offer flexibility for a variety of connections. The
TM4C1294NCPDT GPIO module is comprised of 15 physical GPIO blocks, each corresponding to
an individual GPIO port. The GPIO module is FiRM-compliant (compliant to the ARM Foundation
IP for Real-Time Microcontrollers specification) and supports 0-90 programmable input/output pins.
The number of GPIOs available depends on the peripherals being used (see “Signal
Tables” on page 1772 for the signals available to each GPIO pin).
■ Up to 90 GPIOs, depending on configuration
■ Highly flexible pin muxing allows use as GPIO or one of several peripheral functions
■ 3.3-V-tolerant in input configuration
■ Advanced High Performance Bus accesses all ports:
– Ports A-H and J; Ports K-N and P-Q
■ Fast toggle capable of a change every clock cycle for ports on AHB
■ Programmable control for GPIO interrupts
– Interrupt generation masking
– Edge-triggered on rising, falling, or both
– Level-sensitive on High or Low values
– Per-pin interrupts available on Port P and Port Q
73June 18, 2014
Texas Instruments-Production Data
Tiva
™
TM4C1294NCPDT Microcontroller
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