Register 34: Ethernet MAC Power Domain Status (EMACPDS), offset 0x288
This register provides the status of power to the EMAC SRAM memory array.
Note: The EMAC memory array does not support retention and can only be turned ON and OFF.
Memory array OFF is supported only when the power domain is off. If the memory array is
currently turned on (PWRCTL = 0x3) and the power control to the EMAC is subsequently
removed by clearing the P0 bit of the PCEMAC register, the event causes the memory array
to turn off and the MEMSTAT bit in the EMACPDS register to be 0x0 (array OFF).
Ethernet MAC Power Domain Status (EMACPDS)
Base 0x400F.E000
Offset 0x288
Type RO, reset 0x0000.003F
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
PWRSTATMEMSTATreservedreserved
ROROROROROROROROROROROROROROROROType
1111110000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved31:6
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x3ROreserved5:4
Memory Array Power Status
Displays status of EMAC SRAM memory
DescriptionValue
Array OFF0x0
Reserved0x1-0x2
Array On0x3
0x3ROMEMSTAT3:2
Power Domain Status
DescriptionValue
OFF0x0
Reserved0x1-0x2
ON0x3
0x3ROPWRSTAT1:0
June 18, 2014314
Texas Instruments-Production Data
System Control
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