Register 18: GPIO Digital Enable (GPIODEN), offset 0x51C
Note: Pins configured as digital inputs are Schmitt-triggered.
The GPIODEN register is the digital enable register. By default, all GPIO signals except those listed
below are configured out of reset to be undriven (tristate). Their digital function is disabled; they do
not drive a logic value on the pin and they do not allow the pin voltage into the GPIO receiver. To
use the pin as a digital input or output (either GPIO or alternate function), the corresponding GPIODEN
bit must be set.
Important: The table below shows special consideration GPIO pins. Most GPIO pins are configured
as GPIOs and tri-stated by default (GPIOAFSEL=0, GPIODEN=0, GPIOPDR=0,
GPIOPUR=0, and GPIOPCTL=0). Special consideration pins may be programed to a
non-GPIO function or may have special commit controls out of reset. In addition, a
Power-On-Reset (POR) returns these GPIO to their original special consideration state.
Table 10-11. GPIO Pins With Special Considerations
GPIOCRGPIOPCTLGPIOPURGPIOPDRGPIODENGPIOAFSELDefault Reset
State
GPIO Pins
00x11011JTAG/SWDPC[3:0]
00x00000GPIO
a
PD[7]
00x00000GPIO
a
PE[7]
a. This pin is configured as a GPIO by default but is locked and can only be reprogrammed by unlocking the
pin in the GPIOLOCK register and uncommitting it by setting the GPIOCR register.
The GPIO commit control registers provide a layer of protection against accidental
programming of critical hardware signals including the GPIO pins that can function as
JTAG/SWD signals and the NMI signal. The commit control process must be followed
for these pins, even if they are programmed as alternate functions other than JTAG/SWD
or NMI; see “Commit Control” on page 752.
Note: If the device fails initialization during reset, the hardware toggles the TDO output
as an indication of failure. Thus, during board layout, designers should not
designate the TDO pin as a GPIO in sensitive applications where the possibility
of toggling could affect the design.
Note: The GPIO commit control registers provide a layer of protection against accidental
programming of critical hardware peripherals. Protection is provided for the GPIO pins that
can be used as the four JTAG/SWD pins and the NMI pin (see “Signal Tables” on page 1772
for pin numbers). Writes to protected bits of the GPIO Alternate Function Select
(GPIOAFSEL) register (see page 770), GPIO Pull Up Select (GPIOPUR) register (see
page 776), GPIO Pull-Down Select (GPIOPDR) register (see page 778), and GPIO Digital
Enable (GPIODEN) register (see page 781) are not committed to storage unless the GPIO
Lock (GPIOLOCK) register (see page 783) has been unlocked and the appropriate bits of
the GPIO Commit (GPIOCR) register (see page 784) have been set.
781June 18, 2014
Texas Instruments-Production Data
Tiva
™
TM4C1294NCPDT Microcontroller
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