Texas Instruments TM4C1294NCPDT User Manual

Register 6: I
2
C Master Raw Interrupt Status (I2CMRIS), offset 0x014
This register specifies whether an interrupt is pending.
I2C Master Raw Interrupt Status (I2CMRIS)
I2C 0 base: 0x4002.0000
I2C 1 base: 0x4002.1000
I2C 2 base: 0x4002.2000
I2C 3 base: 0x4002.3000
I2C 4 base: 0x400C.0000
I2C 5 base: 0x400C.1000
I2C 6 base: 0x400C.2000
I2C 7 base: 0x400C.3000
I2C 8 base: 0x400B.8000
I2C 9 base: 0x400B.9000
Offset 0x014
Type RO, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
RISCLKRIS
DMARXRISDMATXRIS
NACKRIS
STARTRIS
STOPRIS
ARBLOSTRIS
TXRISRXRISTXFERISRXFFRISreserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved31:12
Receive FIFO Full Raw Interrupt Status
DescriptionValue
No interrupt0
The Receive FIFO Full interrupt is pending.1
This bit is cleared by writing a 1 to the RXFFIC bit in the I2CMICR
register.
0RORXFFRIS11
Transmit FIFO Empty Raw Interrupt Status
DescriptionValue
No interrupt0
The Transmit FIFO Empty interrupt is pending.1
This bit is cleared by writing a 1 to the TXFEIC bit in the I2CMICR
register.
Note that if we clear the TXFERIS interrupt (by setting the TXFEIC bit)
when the TX FIFO is empty, the TXFERIS interrupt does not reassert
even though the TX FIFO remains empty in this situation.
0ROTXFERIS10
June 18, 20141318
Texas Instruments-Production Data
Inter-Integrated Circuit (I
2
C) Interface

Texas Instruments TM4C1294NCPDT Specifications

General

Brand	Texas Instruments
Model	TM4C1294NCPDT
Category	Microcontrollers
Language	English