Register 14: DMA Channel Enable Set (DMAENASET), offset 0x028
Each bit of the DMAENASET register represents the corresponding µDMA channel. Setting a bit
enables the corresponding µDMA channel. Reading the register returns the enable status of the
channels. If a channel is enabled but the request mask is set (DMAREQMASKSET), then the
channel can be used for software-initiated transfers.
DMA Channel Enable Set (DMAENASET)
Base 0x400F.F000
Offset 0x028
Type RW, reset 0x0000.0000
16171819202122232425262728293031
SET[n]
RWRWRWRWRWRWRWRWRWRWRWRWRWRWRWRWType
0000000000000000Reset
0123456789101112131415
SET[n]
RWRWRWRWRWRWRWRWRWRWRWRWRWRWRWRWType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Channel [n] Enable Set
DescriptionValue
µDMA Channel [n] is disabled.0
µDMA Channel [n] is enabled.1
Bit 0 corresponds to channel 0. A bit can only be cleared by setting the
corresponding CLR[n] bit in the DMAENACLR register or when the
end of a µDMA transfer occurs.
0x0000.0000RWSET[n]31:0
721June 18, 2014
Texas Instruments-Production Data
Tiva
™
TM4C1294NCPDT Microcontroller
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