Texas Instruments TM4C1294NCPDT User Manual

Table 20-13. Enhanced Received Descriptor 4 (RDES4) (continued)
DescriptionBit
IP Payload Type
These bits indicate the type of payload encapsulated in the IP datagram processed by the Receive Checksum
Offload Engine (COE). The COE sets this field to 0x0 if it does not process the IP datagram's payload due to
an IP header error or fragmented IP packet.
■ 0x0= Unknown or did not process IP payload
■ 0x1= UDP
■ 0x2= TCP
■ 0x3= ICMP
■ 0x4 to 0x7= Reserved
This bit is valid when either Bit 7 or Bit 6 is set.
2:0
Table 20-14. Enhanced Receive Descriptor 6 (RDES6)
DescriptionBit
RTSL: Receive Frame Timestamp Low
This field is updated by the DMA with the least significant 32 bits of the timestamp captured for the
corresponding receive frame. This field is updated by the DMA only for the last descriptor of the receive
frame which is indicated by Last Descriptor status bit (RDES0[8]).
31:0
Table 20-15. Enhanced Receive Descriptor 7 (RDES7)
DescriptionBit
RTSH: Receive Frame Timestamp High
This field is updated by DMA with the most significant 32 bits of the timestamp captured for the corresponding
receive frame. This field is updated by DMA only for the last descriptor of the receive frame which is indicated
by Last Descriptor status bit (RDES0[8]).
31:0
20.3.2.6 DMA Transmission Operation
The following sections describe the modes of the transmit operation.
TX DMA Default Operation
The TX DMA engine in default mode, operates as follows:
1. The CPU configures the transmit descriptor (TDES0-TDES3) and sets the OWN bit (TDES0[31])
after setting up the corresponding data buffers with the Ethernet frame.
2. When the ST bit of the Ethernet MAC DMA Operation Mode (EMACDMAOPMODE) register,
offset 0xC18, is set, the DMA enters the RUN state.
3. While in RUN state, the DMA polls the Transmit Descriptor list for frames requiring transmission.
After polling starts, it continues in either sequential descriptor ring order or chained order. If the
DMA detects a descriptor flagged as owned by the CPU (TDES0[31]=0), or if an error condition
occurs, transmission is suspended and both the Transmit Buffer Unavailable (TU) bit and the
Normal Interrupt Summary (NIS) bit are set in the Ethernet MAC DMA Interrupt Status
(EMACDMARIS) register, offset 0xC14. The transmit engine the proceeds to Step 9.
June 18, 20141424
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Ethernet Controller

Texas Instruments TM4C1294NCPDT Specifications

General

Brand	Texas Instruments
Model	TM4C1294NCPDT
Category	Microcontrollers
Language	English