4. If the acquired descriptor is flagged as owned by the DMA (TDES0[31]=1), the DMA decodes
the transmit data buffer address from the acquired descriptor.
5. If the acquired descriptor is flagged as owned by DMA (TDES0[31] = 1), the DMA decodes the
Transmit Data Buffer address from the acquired descriptor.
6. The DMA fetches the transmit data from system memory and transfers the data to the TX/RX
Controller for transmission.
7. If the Ethernet frame is stored over data buffers in multiple descriptors, the DMA closes the
intermediate descriptor and fetches the next descriptor. Steps 3, 4, and 5 are repeated until the
end of the Ethernet frame data is transferred to the TX/RX Controller.
8. When frame transmission is complete, if IEEE 1588 timestamping was enabled for the frame
(as indicated in the transmit status) the timestamp value is written to the transmit descriptor
(TDES6 and TDES7) that contains the end-of-frame buffer. The status information is then written
to transmit descriptor TDES0. Because the OWN bit is cleared during this step, the CPU now
owns this descriptor. If timestamping was not enabled for this frame, the DMA does not alter
the contents of TDES6 and TDES7.
9. The Transmit Interrupt (TI) bit is set in the EMACDMARIS register after transmission completion
of a frame that has Interrupt on Completion set in its last descriptor. The Interrupt on Completion
bit resides in TDES0[30]. The DMA engine then returns to Step 3.
10. In the suspend state, the DMA tries to reacquire the descriptor (and thereby return to Step 3)
when it receives a transmit poll demand in the Ethernet MAC Transmit Poll Demand
(EMACTXPOLLD) register, offset 0xC04, and the Underflow Interrupt Status (UNF) bit is cleared
in the EMACDMARIS register. If the CPU stopped the DMA by clearing the ST bit of the
EMACDMAOPMODE register, the DMA enters the STOP state.
Figure 20-5 on page 1426 shows the flow for the TX DMA default operation.
1425June 18, 2014
Texas Instruments-Production Data
Tiva
™
TM4C1294NCPDT Microcontroller
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