Texas Instruments TM4C1294NCPDT - Register 32: Ethernet MAC Receive Frame Count for Good and Bad Frames (EMACRXCNTGB), Offset 0 X180

Register 32: Ethernet MAC Receive Frame Count for Good and Bad Frames
(EMACRXCNTGB), offset 0x180
This register maintains the number of received good and bad frames.
Note: This counter is reset to all zeros by setting the CNTRST bit in the Ethernet MAC MMC
Control (EMACMMCCTRL), offset 0x100.
Ethernet MAC Receive Frame Count for Good and Bad Frames (EMACRXCNTGB)
Base 0x400E.C000
Offset 0x180
Type RO, reset 0x0000.0000
16171819202122232425262728293031
RXFRMGB
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
RXFRMGB
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
This field indicates the number of received good and bad frames.0x0RORXFRMGB31:0
1527June 18, 2014
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TM4C1294NCPDT Microcontroller