DescriptionResetTypeNameBit/Field
Disable Write Buffer
DescriptionValue
No effect.0
Disables write buffer use during default memory map accesses.
In this situation, all bus faults are precise bus faults but
performance is decreased because any store to memory must
complete before the processor can execute the next instruction.
1
Note: This bit only affects write buffers implemented in the
Cortex-M4 processor.
0RWDISWBUF1
Disable Interrupts of Multiple Cycle Instructions
DescriptionValue
No effect.0
Disables interruption of load multiple and store multiple
instructions. In this situation, the interrupt latency of the
processor is increased because any LDM or STM must complete
before the processor can stack the current state and enter the
interrupt handler.
1
0RWDISMCYC0
165June 18, 2014
Texas Instruments-Production Data
Tiva
™
TM4C1294NCPDT Microcontroller
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