Register 26: GPTM ADC Event (GPTMADCEV), offset 0x070
This register allows software to enable/disable GPTM ADC trigger events. Setting a bit enables the
corresponding ADC trigger, while clearing a bit disables it.
GPTM ADC Event (GPTMADCEV)
16/32-bit Timer 0 base: 0x4003.0000
16/32-bit Timer 1 base: 0x4003.1000
16/32-bit Timer 2 base: 0x4003.2000
16/32-bit Timer 3 base: 0x4003.3000
16/32-bit Timer 4 base: 0x4003.4000
16/32-bit Timer 5 base: 0x4003.5000
16/32-bit Timer 6 base: 0x400E.0000
16/32-bit Timer 7 base: 0x400E.1000
Offset 0x070
Type RW, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
TATOADCEN
CAMADCENCAEADCENRTCADCENTAMADCEN
reserved
TBTOADCEN
CBMADCENCBEADCENTBMADCEN
reserved
RWRWRWRWRWRORORORWRWRWRWROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved31:12
GPTM B Mode Match Event ADC Trigger Enable
When this bit is enabled, a a trigger pulse is sent to the ADC when a
mode match has occurred.
DescriptionValue
Timer B Mode Match ADC trigger is disabled.0
Timer B Mode Match ADC trigger is enabled.1
0RWTBMADCEN11
GPTM B Capture Event ADC Trigger Enable
When this bit is enabled, a trigger pulse is sent to the ADC when a
capture event has occurred.
DescriptionValue
Timer B Capture Event ADC trigger is disabled.0
Timer B Capture Event ADC trigger is enabled.1
0RWCBEADCEN10
GPTM B Capture Match Event ADC Trigger Enable
When this bit is enabled, a trigger signal is sent to the ADC when a
capture match event has occurred.
DescriptionValue
Timer B Capture Match ADC trigger is disabled.0
Timer B Capture Match ADC trigger is enabled.1
0RWCBMADCEN9
June 18, 20141022
Texas Instruments-Production Data
General-Purpose Timers
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