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Texas Instruments TM4C1294NCPDT User Manual

Texas Instruments TM4C1294NCPDT
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Register 56: PWM0 Dead-Band Rising-Edge Delay (PWM0DBRISE), offset
0x06C
Register 57: PWM1 Dead-Band Rising-Edge Delay (PWM1DBRISE), offset
0x0AC
Register 58: PWM2 Dead-Band Rising-Edge Delay (PWM2DBRISE), offset
0x0EC
Register 59: PWM3 Dead-Band Rising-Edge Delay (PWM3DBRISE), offset
0x12C
The PWMnDBRISE register contains the number of clock cycles to delay the rising edge of the
pwmA signal when generating the pwmA' signal. If the dead-band generator is disabled through the
PWMnDBCTL register, this register is ignored. If the value of this register is larger than the width
of a High pulse on the pwmA signal, the rising-edge delay consumes the entire High time of the
signal, resulting in no High time on the output. Care must be taken to ensure that the pwmA High
time always exceeds the rising-edge delay.
If the Dead-Band Rising-Edge Delay mode is immediate (based on the DBRISEUPD field encoding
in the PWMnCTL register), the 12-bit RISEDELAY value is used immediately. If the update mode
is locally synchronized, this value is used the next time the counter reaches zero. If the update mode
is globally synchronized, this value is used the next time the counter reaches zero after a synchronous
update has been requested through the PWM Master Control (PWMCTL) register (see page 1683).
If this register is rewritten before the actual update occurs, the previous value is never used and is
lost.
PWMn Dead-Band Rising-Edge Delay (PWMnDBRISE)
PWM0 base: 0x4002.8000
Offset 0x06C
Type RW, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
RISEDELAYreserved
RWRWRWRWRWRWRWRWRWRWRWRWROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0000.0ROreserved31:12
Dead-Band Rise Delay
The number of clock cycles to delay the rising edge of pwmA' after the
rising edge of pwmA.
0x000RWRISEDELAY11:0
1731June 18, 2014
Texas Instruments-Production Data
Tiva
TM4C1294NCPDT Microcontroller

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Texas Instruments TM4C1294NCPDT Specifications

General IconGeneral
BrandTexas Instruments
ModelTM4C1294NCPDT
CategoryMicrocontrollers
LanguageEnglish

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