Register 135: Ethernet PHY Deep-Sleep Mode Clock Gating Control
(DCGCEPHY), offset 0x830
The DCGCEPHY register provides software the capability to enable and disable the PHY module
in deep-sleep mode. When enabled, a module is provided a clock. When disabled, the clock is
disabled to save power.
Important: This register should be used to control the clocking for the PHY module.
Ethernet PHY Deep-Sleep Mode Clock Gating Control (DCGCEPHY)
Base 0x400F.E000
Offset 0x830
Type RW, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
D0reserved
RWROROROROROROROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved31:1
PHY Module Deep-Sleep Mode Clock Gating Control
DescriptionValue
PHY module is disabled in deep-sleep mode.0
Enable and provide a clock to the PHY module in deep-sleep
mode.
1
0RWD00
June 18, 2014442
Texas Instruments-Production Data
System Control
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