Register 11: GPTM Timer B Interval Load (GPTMTBILR), offset 0x02C
When the timer is counting down, this register is used to load the starting count value into the timer.
When the timer is counting up, this register sets the upper bound for the timeout event.
When a GPTM is configured to one of the 32-bit modes, the contents of bits 15:0 in this register are
loaded into the upper 16 bits of the GPTMTAILR register. Reads from this register return the current
value of Timer B and writes are ignored. In a 16-bit mode, bits 15:0 are used for the load value. Bits
31:16 are reserved in both cases.
GPTM Timer B Interval Load (GPTMTBILR)
16/32-bit Timer 0 base: 0x4003.0000
16/32-bit Timer 1 base: 0x4003.1000
16/32-bit Timer 2 base: 0x4003.2000
16/32-bit Timer 3 base: 0x4003.3000
16/32-bit Timer 4 base: 0x4003.4000
16/32-bit Timer 5 base: 0x4003.5000
16/32-bit Timer 6 base: 0x400E.0000
16/32-bit Timer 7 base: 0x400E.1000
Offset 0x02C
Type RW, reset 0x0000.FFFF
16171819202122232425262728293031
TBILR
RWRWRWRWRWRWRWRWRWRWRWRWRWRWRWRWType
0000000000000000Reset
0123456789101112131415
TBILR
RWRWRWRWRWRWRWRWRWRWRWRWRWRWRWRWType
1111111111111111Reset
DescriptionResetTypeNameBit/Field
GPTM Timer B Interval Load Register
Writing this field loads the counter for Timer B. A read returns the current
value of GPTMTBILR.
When a 16/32-bit GPTM is in 32-bit mode, writes are ignored, and reads
return the current value of GPTMTBILR.
0x0000.FFFFRWTBILR31:0
1005June 18, 2014
Texas Instruments-Production Data
Tiva
™
TM4C1294NCPDT Microcontroller
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