Register 2: QSSI Control 1 (SSICR1), offset 0x004
The SSICR1 register contains bit fields that control various functions within the QSSI module. Master
and slave mode functionality is controlled by this register.
QSSI Control 1 (SSICR1)
QSSI0 base: 0x4000.8000
QSSI1 base: 0x4000.9000
QSSI2 base: 0x4000.A000
QSSI3 base: 0x4000.B000
Offset 0x004
Type RW, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
LBMSSEMSreservedMODEDIRHSCLKEN
FSSHLDFRM
EOMreserved
RWRWRWRORORORWRWRWRWRWRWROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0000.0ROreserved31:12
Stop Frame (End of Message)
This bit is applicable when MODE is set to Advanced, Bi- or Quad- SSI.
This bit is inserted into bit 12 of the TXFIFO data entry by the QSSI
module.
DescriptionValue
No change is transmission status.0
End of message (Stop Frame).1
0RWEOM11
FSS Hold Frame
DescriptionValue
Pulse SSInFss at every byte (the DSS bit in the SSICR0 register
must be set to 0x7 (data size 8 bits) in this configuration)
0
Hold SSInFss for the whole frame1
0RWFSSHLDFRM10
High Speed Clock Enable
High speed clock enable is available only when operating as a master.
DescriptionValue
Use Input Clock0
Use High Speed Clock1
Note: For proper functionality of high speed mode, the HSCLKEN
bit in the SSICR1 register should be set before any SSI data
transfer or after applying a reset to the QSSI module. In
addition, the SSE bit must be set to 0x1 before the HSCLKEN
bit is set.
0RWHSCLKEN9
1247June 18, 2014
Texas Instruments-Production Data
Tiva
™
TM4C1294NCPDT Microcontroller
To Next Page
Loading...
Need help?
General
