The size of the FIFOs must be taken into consideration when configuring the µDMA to transfer data
to and from the EPI. The arbitration size should be 4 or less when writing to EPI address space and
8 or less when reading from EPI address space.
11.4 Initialization and Configuration
To enable and initialize the EPI controller, the following steps are necessary:
1. Enable the EPI module using the RCGCEPI register. See page 386.
2. Enable the clock to the appropriate GPIO module via the RCGCGPIO register. See page 382.
To find out which GPIO port to enable, refer to “Signal Description” on page 817.
3. Set the GPIO AFSEL bits for the appropriate pins. See page 770. To determine which GPIOs to
configure, see Table 26-4 on page 1797.
4. Configure the GPIO current level and/or slew rate as specified for the mode selected. See
page 772 and page 780.
5. Configure the PMCn fields in the GPIOPCTL register to assign the EPI signals to the appropriate
pins. See page 787 and Table 26-5 on page 1808.
6. Select the mode for the EPI block to SDRAM, HB8, HB16, or general parallel use, using the
MODE field in the EPI Configuration (EPICFG) register. Set the mode-specific details (if needed)
using the appropriate mode configuration EPI Host Bus Configuration (EPIHBnCFGn) registers
for the desired chip-select configuration. Set the EPI Main Baud Rate (EPIBAUD) and EPI
Main Baud Rate 2 (EPIBAUD2) register if the baud rate must be slower than the system clock
rate.
7. Configure the address mapping using the EPI Address Map (EPIADDRMAP) register. The
selected start address and range is dependent on the type of external device and maximum
address (as appropriate). For example, for a 512-megabit SDRAM, program the ERADR field to
0x1 for address 0x6000.0000 or 0x2 for address 0x8000.0000; and program the ERSZ field to
0x3 for 256 MB. If using General-Purpose mode and no address at all, program the EPADR field
to 0x1 for address 0xA000.0000 or 0x2 for address 0xC000.0000; and program the EPSZ field
to 0x0 for 256 bytes.
8. To read or write directly, use the mapped address area (configured with the EPIADDRMAP
register). Up to 4 or 5 writes can be performed at once without blocking. Each read is blocked
until the value is retrieved.
9. To perform a non-blocking read, see “Non-Blocking Reads” on page 819.
Note: The application should not attempt to access externally until eight system clock cycles after
the EPI has been fully configured.
Note: Once a MODE field has been programmed in the EPICFG register, the application should
reset all configuration registers before re-programming to a new MODE value.
The following sub-sections describe the initialization and configuration for each of the modes of
operation. Care must be taken to initialize everything properly to ensure correct operation. Control
of the GPIO states is also important, as changes may cause the external device to interpret pin
states as actions or commands (see “Register Descriptions” on page 758). Normally, a pull-up or
pull-down is needed on the board to at least control the chip-select or chip-enable as the
TM4C1294NCPDT GPIOs come out of reset in tri-state.
821June 18, 2014
Texas Instruments-Production Data
Tiva
™
TM4C1294NCPDT Microcontroller
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