Register 175: Analog-to-Digital Converter Peripheral Ready (PRADC), offset
0xA38
The PRADC register indicates whether the ADC modules are ready to be accessed by software
following a change in status of power, Run mode clocking, or reset. A power change is initiated if
the corresponding PCADC bit is changed from 0 to 1. A Run mode clocking change is initiated if
the corresponding RCGCADC bit is changed. A reset change is initiated if the corresponding SRADC
bit is changed from 0 to 1.
The PRADC bit is cleared on any of the above events and is not set again until the module is
completely powered, enabled, and internally reset.
Analog-to-Digital Converter Peripheral Ready (PRADC)
Base 0x400F.E000
Offset 0xA38
Type RO, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
R0R1reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved31:2
ADC Module 1 Peripheral Ready
DescriptionValue
ADC module 1 is not ready for access. It is unclocked,
unpowered, or in the process of completing a reset sequence.
0
ADC module 1 is ready for access.1
0ROR11
ADC Module 0 Peripheral Ready
DescriptionValue
ADC module 0 is not ready for access. It is unclocked,
unpowered, or in the process of completing a reset sequence.
0
ADC module 0 is ready for access.1
0ROR00
515June 18, 2014
Texas Instruments-Production Data
Tiva
™
TM4C1294NCPDT Microcontroller
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