value, and continues counting down. In Count-Up/Down mode, the timer counts from zero up to the
load value, back down to zero, back up to the load value, and so on. Generally, Count-Down mode
is used for generating left- or right-aligned PWM signals, while the Count-Up/Down mode is used
for generating center-aligned PWM signals.
The timers output three signals that are used in the PWM generation process: the direction signal
(this is always Low in Count-Down mode, but alternates between Low and High in Count-Up/Down
mode), a single-clock-cycle-width High pulse when the counter is zero, and a single-clock-cycle-width
High pulse when the counter is equal to the load value. Note that in Count-Down mode, the zero
pulse is immediately followed by the load pulse. In the figures in this chapter, these signals are
labelled "dir," "zero," and "load."
23.3.3 PWM Comparators
Each PWM generator has two comparators that monitor the value of the counter; when either
comparator matches the counter, they output a single-clock-cycle-width High pulse, labeled "cmpA"
and "cmpB" in the figures in this chapter. When in Count-Up/Down mode, these comparators match
both when counting up and when counting down, and thus are qualified by the counter direction
signal. These qualified pulses are used in the PWM generation process. If either comparator match
value is greater than the counter load value, then that comparator never outputs a High pulse.
Figure 23-3 on page 1674 shows the behavior of the counter and the relationship of these pulses
when the counter is in Count-Down mode. Figure 23-4 on page 1674 shows the behavior of the counter
and the relationship of these pulses when the counter is in Count-Up/Down mode. In these figures,
the following definitions apply:
■ LOAD is the value in the PWMnLOAD register
■ COMPA is the value in the PWMnCMPA register
■ COMPB is the value in the PWMnCMPB register
■ 0 is the value zero
■ load is the internal signal that has a single-clock-cycle-width High pulse when the counter is
equal to the load value
■ zero is the internal signal that has a single-clock-cycle-width High pulse when the counter is zero
■ cmpA is the internal signal that has a single-clock-cycle-width High pulse when the counter is
equal to COMPA
■ cmpB is the internal signal that has a single-clock-cycle-width High pulse when the counter is
equal to COMPB
■ dir is the internal signal that indicates the count direction
1673June 18, 2014
Texas Instruments-Production Data
Tiva
™
TM4C1294NCPDT Microcontroller
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