Table 17-4. Legacy Mode TI, Freescale SPI Frame Format Features (continued)
Freescale SPI ModeTI ModeFeature
Master 1:2
Slave 1:12
Master 1:2
Slave 1:12
Frequency (system clock : SSInCLK)
For Advanced, Bi- and Quad-SSI modes using the Freescale SPI Format or the Bi- and Quad-SSI
modes using the TI format, the following features are supported:
■ Frame Hold
■ High Speed (Master RX Only)
■ SPO/SPH Configuration with SPO=0 and SPH=0 only allowed
■ Frequency (system clock : SSInCLK):
– Master 1:2
– Slave 1:12
17.3.7.1 Texas Instruments Synchronous Serial Frame Format
Figure 17-2 on page 1234 shows the Texas Instruments synchronous serial frame format for a single
transmitted frame.
Figure 17-2. TI Synchronous Serial Frame Format (Single Transfer)
SSInClk
SSInFss
SSInTx/SSInRx
MSB LSB
4 to 16 bits
In this mode, SSInClk and SSInFss are forced Low, and the transmit data line SSInDAT0/SSInTX
is tristated whenever the QSSI is idle. Once the bottom entry of the transmit FIFO contains data,
SSInFss is pulsed High for one SSInClk period. The value to be transmitted is also transferred
from the transmit FIFO to the serial shift register of the transmit logic. On the next rising edge of
SSInClk, the MSB of the 4 to 16-bit data frame is shifted out on the SSInDAT0/SSInTX pin.
Likewise, the MSB of the received data is shifted onto the SSInDAT1/SSInRX pin by the off-chip
serial slave device.
Both the QSSI and the off-chip serial slave device then clock each data bit into their serial shifter
on each falling edge of SSInClk. The received data is transferred from the serial shifter to the
receive FIFO on the first rising edge of SSInClk after the LSB has been latched.
Figure 17-3 on page 1235 shows the Texas Instruments synchronous serial frame format when
back-to-back frames are transmitted.
June 18, 20141234
Texas Instruments-Production Data
Quad Synchronous Serial Interface (QSSI)
To Next Page
Loading...
Need help?
General
