Register 4: Interrupt 0-31 Set Enable (EN0), offset 0x100
Register 5: Interrupt 32-63 Set Enable (EN1), offset 0x104
Register 6: Interrupt 64-95 Set Enable (EN2), offset 0x108
Register 7: Interrupt 96-113 Set Enable (EN3), offset 0x10C
Note: This register can only be accessed from privileged mode.
The ENn registers enable interrupts and show which interrupts are enabled. Bit 0 of EN0 corresponds
to Interrupt 0; bit 31 corresponds to Interrupt 31. Bit 0 of EN1 corresponds to Interrupt 32; bit 31
corresponds to Interrupt 63. Bit 0 of EN2 corresponds to Interrupt 64; bit 31 corresponds to Interrupt
95. Bit 0 of EN3 corresponds to Interrupt 96; bit 17 corresponds to Interrupt 113.
See Table 2-9 on page 116 for interrupt assignments.
If a pending interrupt is enabled, the NVIC activates the interrupt based on its priority. If an interrupt
is not enabled, asserting its interrupt signal changes the interrupt state to pending, but the NVIC
never activates the interrupt, regardless of its priority.
Interrupt 0-31 Set Enable (EN0)
Base 0xE000.E000
Offset 0x100
Type RW, reset 0x0000.0000
16171819202122232425262728293031
INT
RWRWRWRWRWRWRWRWRWRWRWRWRWRWRWRWType
0000000000000000Reset
0123456789101112131415
INT
RWRWRWRWRWRWRWRWRWRWRWRWRWRWRWRWType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Interrupt Enable
DescriptionValue
On a read, indicates the interrupt is disabled.
On a write, no effect.
0
On a read, indicates the interrupt is enabled.
On a write, enables the interrupt.
1
A bit can only be cleared by setting the corresponding INT[n] bit in
the DISn register.
0x0000.0000RWINT31:0
June 18, 2014154
Texas Instruments-Production Data
Cortex-M4 Peripherals
To Next Page
Loading...
Need help?
General
