10.3.4 Commit Control
The GPIO commit control registers provide a layer of protection against accidental programming of
critical hardware peripherals. Protection is provided for the GPIO pins that can be used as the four
JTAG/SWD pins and the NMI pin (see “Signal Tables” on page 1772 for pin numbers). Writes to
protected bits of the GPIO Alternate Function Select (GPIOAFSEL) register (see page 770), GPIO
Pull Up Select (GPIOPUR) register (see page 776), GPIO Pull-Down Select (GPIOPDR) register
(see page 778), and GPIO Digital Enable (GPIODEN) register (see page 781) are not committed to
storage unless the GPIO Lock (GPIOLOCK) register (see page 783) has been unlocked and the
appropriate bits of the GPIO Commit (GPIOCR) register (see page 784) have been set.
10.3.5 Pad Control
The pad control registers allow software to configure the GPIO pads based on the application
requirements. The pad control registers include the GPIODR2R, GPIODR4R,
GPIODR8R,GPIODR12R, GPIOODR, GPIOPUR, GPIOPDR, GPIOSLR, and GPIODEN registers.
These registers control drive strength, open-drain configuration, pull-up and pull-down resistors,
slew-rate control and digital input enable for each GPIO. If 3.3V is applied to a GPIO configured as
an open-drain output, the output voltage will depend on the strength of your pull-up resistor. The
GPIO pad is not electrically configured to output 3.3 V.
Note: Port pins PL6 and PL7 operate as Fast GPIO pads, but have 4-mA drive capability only.
GPIO register controls for drive strength, slew rate and open drain have no effect on these
pins. The registers which have no effect are as follows: GPIODR2R, GPIODR4R,
GPIODR8R, GPIODR12R, GPIOSLR, and GPIOODR.
Note: Port pins PM[7:4] operate as Fast GPIO pads but support only 2-, 4-, 6-, and 8-mA drive
capability. 10- and 12-mA drive are not supported. All standard GPIO register controls,
except for the GPIODR12R register, apply to these port pins.
10.3.5.1 Extended Drive Enable
The GPIO Peripheral Configuration (GPIOPC) register controls the extended drive modes of the
GPIO. When the EDE bit in GPIO Peripheral Properties (GPIOPP) register is set and the EDMn bit
field for a GPIO pin is non-zero in the GPIOPC register, the GPIODRnR registers do not drive their
default value, but instead output an incremental drive strength, which has an additive effect. This
allows for more drive strength possibilities. When the EDE bit is set and the EDMn bit field is non-zero,
the 2 mA driver is always enabled. Any bits enabled in the GPIODR4R register for a pin with a
non-zero EDMn value, add an additional 2 mA. Any bits set in the GPIODR8R add an extra 4 mA of
drive. The GPIODR12R register is only valid when the EDMn value is 0x3. For this encoding, setting
a bit in the GPIODR12R register adds 4 mA of drive to the already existing 8 mA, for a 12 mA drive
strength. To attain a 10-mA drive strength, the pin's GPIODR12R and GPIODR8R register should
be enabled; this would result in the addition of two, 4-mA current drivers to the already enabled
2-mA driver. The table below shows the drive capability options. If EDMn is 0x00, then the GPIODR2R,
GPIODR4R, and GPIODR8R function as stated in their default register description.
Note: A GPIOPC register write must precede the configuration of the GPIODRnR registers in
order for extended drive mode to take effect.
June 18, 2014752
Texas Instruments-Production Data
General-Purpose Input/Outputs (GPIOs)
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