Register 16: Interrupt 0-31 Clear Pending (UNPEND0), offset 0x280
Register 17: Interrupt 32-63 Clear Pending (UNPEND1), offset 0x284
Register 18: Interrupt 64-95 Clear Pending (UNPEND2), offset 0x288
Register 19: Interrupt 96-113 Clear Pending (UNPEND3), offset 0x28C
Note: This register can only be accessed from privileged mode.
The UNPENDn registers show which interrupts are pending and remove the pending state from
interrupts. Bit 0 of UNPEND0 corresponds to Interrupt 0; bit 31 corresponds to Interrupt 31. Bit 0 of
UNPEND1 corresponds to Interrupt 32; bit 31 corresponds to Interrupt 63. Bit 0 of UNPEND2
corresponds to Interrupt 64; bit 31 corresponds to Interrupt 95. Bit 0 of UNPEND3 corresponds to
Interrupt 96; bit 31 corresponds to Interrupt 113.
See Table 2-9 on page 116 for interrupt assignments.
Interrupt 0-31 Clear Pending (UNPEND0)
Base 0xE000.E000
Offset 0x280
Type RW, reset 0x0000.0000
16171819202122232425262728293031
INT
RWRWRWRWRWRWRWRWRWRWRWRWRWRWRWRWType
0000000000000000Reset
0123456789101112131415
INT
RWRWRWRWRWRWRWRWRWRWRWRWRWRWRWRWType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Interrupt Clear Pending
DescriptionValue
On a read, indicates that the interrupt is not pending.
On a write, no effect.
0
On a read, indicates that the interrupt is pending.
On a write, clears the corresponding INT[n] bit in the PEND0
register, so that interrupt [n] is no longer pending.
Setting a bit does not affect the active state of the corresponding
interrupt.
1
0x0000.0000RWINT31:0
157June 18, 2014
Texas Instruments-Production Data
Tiva
™
TM4C1294NCPDT Microcontroller
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