■ Data 1 (32 bits) = 0x0201.0100
■ Data 2 (32 bits) = 0x0D08.0503
■ Data 3 (32 bits) = 0x5937.2215
If the data bytes are correct, then the device is returned to factory condition. During the
return-to-factory settings function, the following events occur:
■ The RAM is erased in the Hibernation module
■ The system SRAM is erased
■ The FMPPEn registers are set to 0xFFFF.FFFF (to allow a Flash erase operation to occur)
■ The EEPROM pages are erased
■ A mass-erase of the flash array occurs
■ The BOOTCFG register is written with 0xFFFF.FFFE
Once the return-to-factory settings sequence is completed, the CDOFF field of the HSSR register is
written with 0x00.0000, indicating a successful completion and activating a system reset.
5.3 Initialization and Configuration
The PLL is configured using direct register writes to the PLLFREQn, MEMTIM0, and PLLSTAT
registers. The steps for initializing the system clock from POR to use the PLL from the main oscillator
is as follows:
1. Once POR has completed, the PIOSC is acting as the system clock.
2. Power up the MOSC by clearing the NOXTAL bit in the MOSCCTL register.
3. If single-ended MOSC mode is required, the MOSC is ready to use. If crystal mode is required,
clear the PWRDN bit and wait for the MOSCPUPRIS bit to be set in the Raw Interrupt Status
(RIS), indicating MOSC crystal mode is ready.
4. Set the OSCSRC field to 0x3 in the RSCLKCFG register at offset 0x0B0.
5. If the application also requires the MOSC to be the deep-sleep clock source, then program the
DSOSCSRC field in the DSCLKCFG register to 0x3.
6. Write the PLLFREQ0 and PLLFREQ1 registers with the values of Q, N, MINT, and MFRAC to
the configure the desired VCO frequency setting.
7. Write the MEMTIM0 register to correspond to the new system clock setting.
8. Wait for the PLLSTAT register to indicate the PLL has reached lock at the new operating point
(or that a timeout period has passed and lock has failed, in which case an error condition exists
and this sequence is abandoned and error processing is initiated).
9. Write the RSCLKCFG register's PSYSDIV value, set the USEPLL bit to enabled, and MEMTIMU
bit.
June 18, 2014246
Texas Instruments-Production Data
System Control
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