Register 27: LDO Deep-Sleep Power Control (LDODPCTL), offset 0x1BC
This register specifies the LDO output voltage in Sleep mode. This register should be configured
while in Run Mode. If the VADJEN bit is set, writes can be made to the VLDO field within the provided
encodings. The following table shows the maximum clock frequencies with respect to LDO Voltage.
Table 5-15. Maximum System Clock and PIOSC Frequency with Respect to LDO Voltage
PIOSCMaximum System Clock FrequencyOperating Voltage (LDO)
16 MHz120 MHz1.2
16 MHz30 MHz0.9
LDO Deep-Sleep Power Control (LDODPCTL)
Base 0x400F.E000
Offset 0x1BC
Type RW, reset 0x0000.0012
16171819202122232425262728293031
reservedVADJEN
RORORORORORORORORORORORORORORORWType
0000000000000000Reset
0123456789101112131415
VLDOreserved
RWRWRWRWRWRWRWRWROROROROROROROROType
0100100000000000Reset
DescriptionResetTypeNameBit/Field
Voltage Adjust Enable
This bit enables the value of the VLDO field to be used to specify the
output voltage of the LDO in Deep-Sleep mode.
DescriptionValue
The LDO output voltage is set to the factory default value in
Deep-Sleep mode. The value of the VLDO field does not affect
the LDO operation.
0
The LDO output value in Deep-Sleep mode is configured by the
value in the VLDO field.
1
0RWVADJEN31
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x000.00ROreserved30:8
303June 18, 2014
Texas Instruments-Production Data
Tiva
™
TM4C1294NCPDT Microcontroller
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