Texas Instruments TM4C1294NCPDT - Register 3: CAN Error Counter (CANERR), Offset 0 X008

Register 3: CAN Error Counter (CANERR), offset 0x008
This register contains the error counter values, which can be used to analyze the cause of an error.
CAN Error Counter (CANERR)
CAN0 base: 0x4004.0000
CAN1 base: 0x4004.1000
Offset 0x008
Type RO, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
TECRECRP
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0000ROreserved31:16
Received Error Passive
DescriptionValue
The Receive Error counter is below the Error Passive
level (127 or less).
0
The Receive Error counter has reached the Error Passive
level (128 or greater).
1
0RORP15
Receive Error Counter
This field contains the state of the receiver error counter (0 to 127).
0x00ROREC14:8
Transmit Error Counter
This field contains the state of the transmit error counter (0 to 255).
0x00ROTEC7:0
1383June 18, 2014
Texas Instruments-Production Data
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TM4C1294NCPDT Microcontroller