7.3.4 Battery Management
Important: System-level factors may affect the accuracy of the low-battery detect circuit. The
designer should consider battery type, discharge characteristics, and a test load during
battery voltage measurements.
The Hibernation module can be independently powered by a battery or an auxiliary power source
using the VBAT pin. The module can monitor the voltage level of the battery and detect when the
voltage drops below V
LOWBAT
. The voltage threshold can be between 1.9 V and 2.5 V and is
configured using the VBATSEL field in the HIBCTL register. The module can also be configured so
that it does not go into Hibernate mode if the battery voltage drops below this threshold. In addition,
battery voltage is monitored while in hibernation, and the microcontroller can be configured to wake
from hibernation if the battery voltage goes below the threshold using the BATWKEN bit in the HIBCTL
register.
The Hibernation module is designed to detect a low-battery condition and set the LOWBAT bit of the
Hibernation Raw Interrupt Status (HIBRIS) register when this occurs. If the VABORT bit in the
HIBCTL register is also set, then the module is prevented from entering Hibernate mode when a
low-battery is detected. The module can also be configured to generate an interrupt for the low-battery
condition (see “Interrupts and Status” on page 548).
7.3.5 Real-Time Clock
The RTC module is designed to keep wall time. The RTC can operate in seconds counter mode or
calendar mode. A 32.768 kHz clock source along with a 15-bit predivider reduces the clock to 1 Hz.
The 1 Hz clock is used to increment the 32-bit counter and keep track of seconds. In calendar mode,
registers are provided which support the tracking of date, month, year and day-of-week. A match
register can be configured to interrupt or wake the system from hibernate. In addition, a software
trim register is implemented to allow the user to compensate for oscillator inaccuracies using software.
7.3.5.1 RTC Counter - Seconds/Subseconds Mode
The clock signal to the RTC is provided by either of the 32.768-kHz clock sources available to the
Hibernation module. The Hibernation RTC Counter (HIBRTCC) register displays the seconds
value. The Hibernation RTC Sub Seconds register (HIBRTCSS) is provided for additional time
resolution of an application requiring less than one-second divisions.
The RTC is enabled by setting the RTCEN bit of the HIBCTL register. The RTCEN bit is also used
along with the CALEN bit in the Hibernation Calendar Control (HIBCALCTL) register to enable
the calender. Thus, if the calendar is enabled, the RTC registers, HIBRTCC, HIBRTCSS, HIBRTCM0
and HIBRTCLD, cannot be used. The RTC counter and sub-seconds counters begin counting
immediately once RTCEN is set. Both counters count up. The RTC continues counting as long as
the RTC is enabled and a valid V
BAT
is present, regardless of whether V
DD
is present or if the device
is in hibernation.
The HIBRTCC register is set by writing the Hibernation RTC Load (HIBRTCLD) register. A write
to the HIBRTCLD register clears the 15-bit sub-seconds counter field, RTCSSC, in the HIBRTCSS
register. To ensure a valid read of the RTC value, the HIBRTCC register should be read first, followed
by a read of the RTCSSC field in the HIBRTCSS register and then a re-read of the HIBRTCC register.
If the two values for the HIBRTCC are equal, the read is valid. By following this procedure, errors
in the application caused by the HIBRTCC register rolling over by a count of 1 during a read of the
RTCSSC field are prevented. The RTC can be configured to generate an alarm by setting the RTCAL0
bit in the HIBIM register. When an RTC match occurs, an interrupt is generated and displayed in
the HIBRIS register. Refer to “RTC Match - Seconds/Subseconds Mode” on page 540 for more
information.
539June 18, 2014
Texas Instruments-Production Data
Tiva
™
TM4C1294NCPDT Microcontroller
To Next Page
Loading...
Need help?
General
