DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:29
Instruction Access Disable
DescriptionValue
Instruction fetches are enabled.0
Instruction fetches are disabled.1
0RWXN28
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved27
Access Privilege
For information on using this bit field, see Table 3-5 on page 141.
0RWAP26:24
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0ROreserved23:22
Type Extension Mask
For information on using this bit field, see Table 3-3 on page 140.
0x0RWTEX21:19
Shareable
For information on using this bit, see Table 3-3 on page 140.
0RWS18
Cacheable
For information on using this bit, see Table 3-3 on page 140.
0RWC17
Bufferable
For information on using this bit, see Table 3-3 on page 140.
0RWB16
Subregion Disable Bits
DescriptionValue
The corresponding subregion is enabled.0
The corresponding subregion is disabled.1
Region sizes of 128 bytes and less do not support subregions. When
writing the attributes for such a region, configure the SRD field as 0x00.
See the section called “Subregions” on page 140 for more information.
0x00RWSRD15:8
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0ROreserved7:6
Region Size Mask
The SIZE field defines the size of the MPU memory region specified by
the MPUNUMBER register. Refer to Table 3-10 on page 199 for more
information.
0x0RWSIZE5:1
June 18, 2014200
Texas Instruments-Production Data
Cortex-M4 Peripherals