DescriptionResetTypeNameBit/Field
PendSV Clear Pending
DescriptionValue
On a write, no effect.0
On a write, removes the pending state from the PendSV
exception.
1
This bit is write only; on a register read, its value is unknown.
0WOUNPENDSV27
SysTick Set Pending
DescriptionValue
On a read, indicates a SysTick exception is not pending.
On a write, no effect.
0
On a read, indicates a SysTick exception is pending.
On a write, changes the SysTick exception state to pending.
1
This bit is cleared by writing a 1 to the PENDSTCLR bit.
0RWPENDSTSET26
SysTick Clear Pending
DescriptionValue
On a write, no effect.0
On a write, removes the pending state from the SysTick
exception.
1
This bit is write only; on a register read, its value is unknown.
0WOPENDSTCLR25
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved24
Debug Interrupt Handling
DescriptionValue
The release from halt does not take an interrupt.0
The release from halt takes an interrupt.1
This bit is only meaningful in Debug mode and reads as zero when the
processor is not in Debug mode.
0ROISRPRE23
Interrupt Pending
DescriptionValue
No interrupt is pending.0
An interrupt is pending.1
This bit provides status for all interrupts excluding NMI and Faults.
0ROISRPEND22
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0ROreserved21:20
June 18, 2014168
Texas Instruments-Production Data
Cortex-M4 Peripherals
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