DescriptionResetTypeNameBit/Field
EN0PPS Output Frequency Control (PPSCTRL) or Command Control
(PPSCMD)
This bit field has two different functions depending on how the PPSEN0
bit is set. See the values in Table 20-24 on page 1549.
If the PPSEN0 bit is set to 0x0, this field functions as a PPS0 output
frequency control (PPSCTRL), which controls the frequency of the output
signal, EN0PPS. The default value of this field is 0x0 and the PPS output
is one pulse every second.
If the PPSEN0 bit is 0x1, this field functions as a flexible output command
control for the EN0PPS signal. Programming the PPSCTRL bit field with
a non-zero value instructs the MAC to initiate an event. When the
command is transferred or synchronized to the PTP clock domain, these
bits are cleared automatically. Software should ensure that these bits
are programmed only when they are "all-zeros."
Note that in the binary rollover mode, the EN0PPS signal has a duty
cycle of 50 percent with these frequencies.
In the digital rollover mode, the EN0PPS signal frequency is an average
number. The actual clock is of different frequency that gets synchronized
every second. For example:
When PPSCTRL =0x1, EN0PPS (1 Hz) has a low period of 537 ms and
a high period of 463 ms.
When PPSCTRL = 0x2, EN0PPS (2 Hz) is a sequence of:
■ One clock of 50 percent duty cycle and 537 ms period
■ Second clock of 463 ms period (268 ms low and 195 ms high)
When PPSCTRL = 0x3, EN0PPS (4 Hz) is a sequence of:
■ Three clocks of 50 percent duty cycle and 268 ms period
■ Fourth clock of 195 ms period (134 ms low and 61 ms high)
This signaling behavior is because of the non-linear toggling of bits in
the digital rollover mode in the Ethernet MAC System Time -
Nanoseconds (EMACTIMNANO) register.
0x0RWPPSCTRL3:0
Table 20-24. PPSCTRL Bit Field Values
DescriptionValue
When the PPSEN0 bit = 0x0, the EN0PPS signal is 1 pulse of the PTP reference clock. every
second.
0x0
When the PPSEN0 bit = 0x1, this encoding indicates no command.
When the PPSEN0 bit = 0x0, the binary rollover is 2 Hz, and the digital rollover is 1 Hz.0x1
When the PPSEN0 bit = 0x1, START single pulse. This command generates a single pulse rising
at the start point defined in the Ethernet MAC Target Time Second/Nanoseconds (EMACTARGX)
registers (MAC offsets 0x71C and 0x720) and a duration defined in the Ethernet MAC PPS0 Width
(EMACPPS0WIDTH) register (offset 0x764).
When the PPSEN0 bit = 0x0, the binary rollover is 4 Hz, and the digital rollover is 2 Hz.0x2
When the PPSEN0 bit = 0x1, START pulse train. This command generates the train of pulses rising
at the start point defined in the Ethernet MAC Target Time Second/Nanoseconds (EMACTARGX)
registers (MAC offsets 0x71C and 0x720) and repeated at an interval defined in the Ethernet MAC
PPS0 Width (EMACPPS0WIDTH) register (offset 0x764). By default, the EN0PPS pulse train is
free-running unless stopped by STOP pulse train at a time or STOP pulse train immediately
command.
When thePPSEN0 bit = 0x0, the binary rollover is 8 Hz, and the digital rollover is 4 Hz,0x3
1549June 18, 2014
Texas Instruments-Production Data
Tiva
™
TM4C1294NCPDT Microcontroller
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