Register 20: PLL Frequency 1 (PLLFREQ1), offset 0x164
This register always contains the current Q and N values presented to the system PLL. If the PLL
is reconfigured, it must go through a relock sequence which takes about 128 PIOSC clocks. When
controlling this register directly, software must change this value while the PLL is powered down.
Writes to PLLFREQ0 are delayed from affecting the PLL until the RSCLKCFG register NEWFREQ
bit is written with a 1.
The MINT and MFRAC fields are present in the PLLFREQ0 register.
PLL Frequency 1 (PLLFREQ1)
Base 0x400F.E000
Offset 0x164
Type RW, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
NreservedQreserved
RWRWRWRWRWRORORORWRWRWRWRWROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0000.0ROreserved31:13
PLL Q Value
This field contains the PLL Q value.
0x0RWQ12:8
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0ROreserved7:5
PLL N Value
This field contains the PLL N value.
0x0RWN4:0
293June 18, 2014
Texas Instruments-Production Data
Tiva
™
TM4C1294NCPDT Microcontroller
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