Register 10: QSSI DMA Control (SSIDMACTL), offset 0x024
The SSIDMACTL register is the µDMA control register.
QSSI DMA Control (SSIDMACTL)
QSSI0 base: 0x4000.8000
QSSI1 base: 0x4000.9000
QSSI2 base: 0x4000.A000
QSSI3 base: 0x4000.B000
Offset 0x024
Type RW, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
RXDMAETXDMAEreserved
RWRWROROROROROROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0000.000ROreserved31:2
Transmit DMA Enable
DescriptionValue
µDMA for the transmit FIFO is disabled.0
µDMA for the transmit FIFO is enabled.1
0RWTXDMAE1
Receive DMA Enable
DescriptionValue
µDMA for the receive FIFO is disabled.0
µDMA for the receive FIFO is enabled.1
0RWRXDMAE0
June 18, 20141260
Texas Instruments-Production Data
Quad Synchronous Serial Interface (QSSI)
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