Register 32: EPI Masked Interrupt Status (EPIMIS), offset 0x218
This register is the masked interrupt status register. On read, it gives the current state of each
interrupt source (read, write, and error) after being masked via the EPIIM register. A write has no
effect.
The values returned are the ANDing of the EPIIM and EPIRIS registers. If a bit is set in this register,
the interrupt is sent to the interrupt controller.
EPI Masked Interrupt Status (EPIMIS)
Base 0x400D.0000
Offset 0x218
Type RO, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
ERRMISRDMISWRMIS
DMARDMISDMAWRMIS
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x000ROreserved31:5
Write uDMA Masked Interrupt Status
DescriptionValue
The write uDMA has not completed or the interrupt is masked.0
The write uDMA has completed and the DMAWRIM bit in the
EPIIM register is set, triggering an interrupt to the interrupt
controller.
1
This bit is cleared by writing a 1 to the DMAWRIC bit in the EPIEISC
register.
0RODMAWRMIS4
Read uDMA Masked Interrupt Status
DescriptionValue
The read uDMA has not completed or the interrupt is masked.0
The read uDMA has completed and the DMAWRIM bit in the
EPIIM register is set, triggering an interrupt to the interrupt
controller.
1
This bit is cleared by writing a 1 to the DMARDIC bit in the EPIEISC
register.
0RODMARDMIS3
911June 18, 2014
Texas Instruments-Production Data
Tiva
™
TM4C1294NCPDT Microcontroller
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