DescriptionResetTypeNameBit/Field
Write Raw Interrupt Status
DescriptionValue
The number of available entries in the WFIFO is above the range
specified by the WRFIFO field in the EPIFIFOLVL register.
0
The number of available entries in the WFIFO is within the
trigger range specified by the WRFIFO field in the EPIFIFOLVL
register.
1
This bit is cleared when the level in the WFIFO is above the trigger point
programmed by the WRFIFO field.
1ROWRRIS2
Read Raw Interrupt Status
DescriptionValue
The number of valid entries in the NBRFIFO is below the trigger
range specified by the RDFIFO field in the EPIFIFOLVL register.
0
The number of valid entries in the NBRFIFO is in the trigger
range specified by the RDFIFO field in the EPIFIFOLVL register.
1
This bit is cleared when the level in the NBRFIFO is below the trigger
point programmed by the RDFIFO field.
0RORDRIS1
Error Raw Interrupt Status
The error interrupt occurs in the following situations:
■ WFIFO Full. For a full WFIFO to generate an error interrupt, the
WFERR bit in the EPIFIFOLVL register must be set.
■ Read Stalled. For a stalled read to generate an error interrupt, the
RSERR bit in the EPIFIFOLVL register must be set.
■ Timeout. If the MAXWAIT field in the EPIHBnCFG register is
configured to a value other than 0, a timeout error occurs when
XFIFO not-ready signals hold a transaction for more than the count
in the MAXWAIT field.
DescriptionValue
An error has not occurred.0
A WFIFO Full, a Read Stalled, or a Timeout error has occurred.1
To determine which error occurred, read the status of the EPI Error
Interrupt Status and Clear (EPIEISC) register. This bit is cleared by
writing a 1 to the bit in the EPIEISC register that caused the interrupt.
0ROERRRIS0
June 18, 2014910
Texas Instruments-Production Data
External Peripheral Interface (EPI)
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