13.3.6 DMA Operation
The timers each have a dedicated μDMA channel and can provide a request signal to the μDMA
controller. Pulse requests are generated by a timer via its own dma_req signal. A dma_done signal
is provided from the µDMA to each timer to indicate transfer completion and trigger a µDMA done
interrupt (DMAnRIS) in the GPTM Raw Interrupt Status Register (GPTMRIS) register. The request
is a burst type and occurs whenever a timer raw interrupt condition occurs. The arbitration size of
the μDMA transfer should be set to the amount of data that should be transferred whenever a timer
event occurs.
For example, to transfer 256 items, 8 items at a time every 10 ms, configure a timer to generate a
periodic timeout at 10 ms. Configure the μDMA transfer for a total of 256 items, with a burst size of
8 items. Each time the timer times out, the μDMA controller transfers 8 items, until all 256 items
have been transferred. Refer to “Micro Direct Memory Access (μDMA)” on page 678 for more details
about programming the μDMA controller.
A GPTM DMA Event (GPTMDMAEV) register is provided to enable the types of events that can
cause a dma_req signal assertion by the timer module. Application software can enable a dma_req
trigger for a match, capture or time-out event for each timer using the GPTMDMAEV register. For
an individual timer, all active timer trigger events that have been enabled through the GPTMDMAEV
register are ORed together to create a single dma_req pulse that is sent to the µDMA. When the
µDMA transfer has completed, a dma_done signal is sent to the timer resulting in a DMAnRIS bit
set in the GPTMRIS register.
13.3.7 ADC Operation
The timer has the capability to trigger the ADC when the TnOTE bit is set in the GPTMCTL register
at offset 0x00C. The GPTM ADC Event (GPTMADCEV) register is additionally provided so that the
type of ADC trigger can be defined. For example, by setting the CBMADCEN bit in the GPTMADCEV
register, a trigger pulse will be sent to the ADC whenever a Capture Match event occurs in GPTM
B. Similar to the µDMA operation, all active trigger events that have also been enabled in the
GPTMADCEV register are ORed together to create an ADC trigger pulse.
13.3.8 Accessing Concatenated 16/32-Bit GPTM Register Values
The GPTM is placed into concatenated mode by writing a 0x0 or a 0x1 to the GPTMCFG bit field in
the GPTM Configuration (GPTMCFG) register. In both configurations, certain 16/32-bit GPTM
registers are concatenated to form pseudo 32-bit registers. These registers include:
■ GPTM Timer A Interval Load (GPTMTAILR) register [15:0], see page 1004
■ GPTM Timer B Interval Load (GPTMTBILR) register [15:0], see page 1005
■ GPTM Timer A (GPTMTAR) register [15:0], see page 1012
■ GPTM Timer B (GPTMTBR) register [15:0], see page 1013
■ GPTM Timer A Value (GPTMTAV) register [15:0], see page 1014
■ GPTM Timer B Value (GPTMTBV) register [15:0], see page 1015
■ GPTM Timer A Match (GPTMTAMATCHR) register [15:0], see page 1006
■ GPTM Timer B Match (GPTMTBMATCHR) register [15:0], see page 1007
June 18, 2014970
Texas Instruments-Production Data
General-Purpose Timers
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