Texas Instruments TM4C1294NCPDT - Register 13: UART Interrupt Clear (UARTICR), Offset 0 X044

Register 13: UART Interrupt Clear (UARTICR), offset 0x044
The UARTICR register is the interrupt clear register. On a write of 1, the corresponding interrupt
(both raw interrupt and masked interrupt, if enabled) is cleared. A write of 0 has no effect.
Note that bits [3:0] are only implemented on UART1. These bits are reserved on UART0 and UART2.
UART Interrupt Clear (UARTICR)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
UART2 base: 0x4000.E000
UART3 base: 0x4000.F000
UART4 base: 0x4001.0000
UART5 base: 0x4001.1000
UART6 base: 0x4001.2000
UART7 base: 0x4001.3000
Offset 0x044
Type W1C, reset 0x0000.0000
16171819202122232425262728293031
DMARXICDMATXICreserved
W1CW1CROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
RIMICCTSMICDCDMICDSRMICRXICTXICRTICFEICPEICBEICOEICEOTIC9BITICreserved
W1CW1CW1CW1CW1CW1CW1CW1CW1CW1CW1CW1CRWROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved31:18
Transmit DMA Interrupt Clear
Writing a 1 to this bit clears the DMATXRIS bit in the UARTRIS register
and the DMATXMIS bit in the UARTMIS register.
0W1CDMATXIC17
Receive DMA Interrupt Clear
Writing a 1 to this bit clears the DMARXRIS bit in the UARTRIS register
and the DMARXMIS bit in the UARTMIS register.
0W1CDMARXIC16
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved15:13
9-Bit Mode Interrupt Clear
Writing a 1 to this bit clears the 9BITRIS bit in the UARTRIS register
and the 9BITMIS bit in the UARTMIS register.
0RW9BITIC12
End of Transmission Interrupt Clear
Writing a 1 to this bit clears the EOTRIS bit in the UARTRIS register
and the EOTMIS bit in the UARTMIS register.
0W1CEOTIC11
Overrun Error Interrupt Clear
Writing a 1 to this bit clears the OERIS bit in the UARTRIS register and
the OEMIS bit in the UARTMIS register.
0W1COEIC10
June 18, 20141206
Texas Instruments-Production Data
Universal Asynchronous Receivers/Transmitters (UARTs)