Table 18-5. Write Field Decoding for I2CMCS[6:0]
Next State Description
I2CMCS[6:0]I2CMSA[0]
Current
State
RUNSTARTSTOPACKHSQCCMDBURSTR/S
START condition followed by TRANSMIT
(master goes to the Master Transmit state).
110X
a
0000
Idle
START condition followed by a TRANSMIT
and STOP condition (master remains in Idle
state).
111X0000
START condition followed by N FIFO-serviced
TRANSMITs (master goes to the Master
Transmit state).
010X0010
START condition followed by N FIFO-serviced
TRANSMITs and STOP condition (master
remains in Idle state).
011X0010
START condition followed by RECEIVE
operation with negative ACK (master goes to
the Master Receive state).
11000001
Quick Command (Send). After Quick
Command is executed, the master returns to
Idle state.
11100100
Quick Command (Receive). After Quick
Command is executed, the master returns to
Idle state.
11100101
START condition followed by RECEIVE and
STOP condition (master remains in Idle state).
11100001
START condition followed by RECEIVE
(master goes to the Master Receive state).
11010001
START condition followed by N FIFO-serviced
RECEIVE operations with a negative ACK on
the last RECEIVE operation (master goes to
the Master Receive state).
01000011
START condition followed by N FIFO-serviced
RECEIVE operations with a negative ACK on
the last RECEIVE and STOP condition (master
remains in Idle state).
01100011
START condition followed by N FIFO-serviced
RECEIVE operations (master goes to the
Master Receive state).
01010011
START/RUN condition where master byte is
sent with no ACK; followed by High Speed
transmit Operation. All subsequent transfers
are carried out using normal transmit
commands.
11001000
RUN/BURST condition where master byte is
sent with no ACK; followed by High Speed
Burst transmit Operation.
00001010
Illegal11110001
Illegal01110001
NOPAll other combinations not listed are non-operations.
June 18, 20141308
Texas Instruments-Production Data
Inter-Integrated Circuit (I
2
C) Interface
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