Texas Instruments TM4C1294NCPDT - Page 1307

DescriptionResetTypeNameBit/Field
I
2
C Master Enable
DescriptionValue
In standard and high speed mode, this encoding means the
master is unable to transmit or receive data.
In Burst mode, this bit is not used and must be set to 0.
0
The master is able to transmit or receive data.
Note that this bit cannot be set in Burst mode. See field decoding
in Table 18-5 on page 1308.
1
Note that the BURST and RUN bits are mutually exclusive.
0WORUN0
The Table 18-5 on page 1308 can be read from left to right to determine the next state after
programming bits in the I2CMSA and I2CMCS registers.
1307June 18, 2014
Texas Instruments-Production Data
Tiva
™
TM4C1294NCPDT Microcontroller