Register 31: EPI Raw Interrupt Status (EPIRIS), offset 0x214
This register is the raw interrupt status register. On a read, it gives the current state of each interrupt
source. A write has no effect.
Note that raw status for read and write is set or cleared based on FIFO fullness as controlled by
EPIFIFOLVL.
Raw status for error is held until the error is cleared by writing to the EPIEISC register.
EPI Raw Interrupt Status (EPIRIS)
Base 0x400D.0000
Offset 0x214
Type RO, reset 0x0000.0004
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
ERRRISRDRISWRRIS
DMARDRISDMAWRRIS
reserved
ROROROROROROROROROROROROROROROROType
0010000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x000ROreserved31:5
Write uDMA Raw Interrupt Status
DescriptionValue
The write uDMA has not completed.0
The write uDMA has completed.1
This bit is cleared by writing a 1 to the DMAWRIC bit in the EPIEISC
register.
0RODMAWRRIS4
Read uDMA Raw Interrupt Status
DescriptionValue
The read uDMA has not completed.0
The read uDMA has completed.1
This bit is cleared by writing a 1 to the DMARDIC bit in the EPIEISC
register.
0RODMARDRIS3
909June 18, 2014
Texas Instruments-Production Data
Tiva
™
TM4C1294NCPDT Microcontroller
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